Services
Digital Frontend
ASIC Design
- SoC architecture and IP micro architecture
- RTL design and development
- SoC and Sub-System integration
- DFT RTL design and integration
- RTL quality checks
- Synthesis, timing, caliber and FEV
- Timing, constraints and constraints validation
- UPF and CLP
ASIC Verification
- Specialized in SoC and IP verification
- Test plan development: requirement analysis, feature and scenarios identification
- SV & UVM based testbench development
- VIP development and integration
- Assertions and Formal verification
- Low power / power aware verification
- Processor verification
- Gate Level Simulations
- Automation and regression management
- Functional and code coverage closure
Post Silicon Validation Support
- ATP and Timeset generation for J750 and Advance Teradyne Testers
- EVCD generation for characterization
- Die Yield Analysis
- Parameterisation tests
- IO leakage
- Analog and Digital RX/TX
- Stuck at patterns
- Sequences to detect PVT corner values for IO calibration
FPGA
- FPGA selection
- Micro-architecture design
- ASIC / IP prototyping and validation with FPGA
- Embedded hardware and software support
- FPGA to FPGA, FPGA to ASIC, ASIC to FPGA conversion
- Board design and bring u
- System integration and validation
- FPGA-SoC design integration
- RTL coding to timing closure & area-driven PnR
- Functional verification
Digital BackEnd
Synthesis - Physical Design
- Setting up the Synthesis flow
- Developing constraints
- Logic and Physical aware synthesis using industry standard tools
RTL to GDS II - Physical Design
- RTL Synthesis (logical & physical aware)
- Library quality checks and IP validation
- Die size estimation (ump and Ball requirement, MFU)
- IO planning, floor planning, partitioning
- Power planning and low power strategy
- Place & Route
- Clock tree synthesis
- Design for manufacture (Metal Fill, Spare Cells, Decap Cells)
- Power analysis (EM/IR)
- Physical verification (DRC, LVS, ERC, ANTENNA, PERC, XOR)
- Low power checks (CLP) & formality (LEC)
- ECO iteration (functional & timing fixes)
Static Timing Analysis
- Setting up the STA flow
- Develop Timing Constraints for Multiple Modes
- Timing analysis for multi modes & multi corners
- SI analysis
- SI Analysis
DFT - Design for Testability
- DFT Implementation
- Scan insertion, BIST Insertion
- Test mode constraints development
- Coverage Improvement
- DFT simulation checks
- Pattern generation and simulation
Analog, Mixed Signal & Technology Foundation
- Circuit design & Characterization
- Process and layout migration
- Analog layout design
- PLL / LVDS / LDO / Bandgap design
- Custom memory and memory compiler
- I/O libraries, RF, SERDES layout
- Standard cell library development
- Physical verification for DRC/LVS
- Automation flow development using EDA tools
- Python / Perl / Tcl scripting
Embedded Systems
- Firmware development
- Device drivers
- Board support packages development
- RTOS
- Debug utilities